Bus operation with integrated circuits in an unpowered state

ABSTRACT

A circuit configuration applicable to systems such as consumer electronics devices enables communication between components such as integrated circuits connected to the bus. According to an embodiment, the RUN power supplies are turned to an OFF state in response to a fault condition. An interface circuit associated with an integrated circuit coupled to the bus controls the loading on the bus caused by the interface circuit and the integrated circuit such that communication between devices on the bus can continue. Therefore, even when a fault condition results in the loss of the RUN power supplies, a command can be transmitted over the bus from a first integrated circuit in a powered state to a second integrated circuit in the powered state while a third integrated circuit connected to the bus is in an unpowered state.

This application claims the benefit under 35 U.S.C. § 365 ofInternational Application PCT/US01/17472, filed May 31, 2001, which waspublished in accordance with PCT Article 21(2) on Dec. 13, 2001 inEnglish; and which claims benefit of U.S. provisional application Ser.No. 60/209,085 filed Jun. 2, 2000.

The present invention relates to an apparatus and method forcommunicating over a bus, and more particularly, to an apparatus andmethod for communicating over a bus connected to a plurality ofintegrated circuits when one or more of the integrated circuits are inan unpowered state.

Electronic systems, such as a television receiver, often include one ormore busses for connecting a plurality of integrated circuits andallowing them to send and receive data between each other. A well knownbus often used in consumer electronic applications is the interintegrated circuit bus (“IIC bus” or “I2C bus”). The IIC bus is a twotransmission medium, bi-directional digital bus that permits two ICs tocommunicate on a bus path at a time. An IC serving in a “master” mode ofoperation, initiates a data transfer operation on the bus and generatesclock signals that permit the data transfer. An IC serving in a “slave”mode of operation is the IC being operated on, or communicated to, bythe master IC, whereby the slave IC is instructed to either send orreceive data. Each IC is assigned a unique address on the bus.

Some systems include a plurality of IIC busses. In such systems, one IICbus generally referred to as a standby (“STBY”) bus is used to transmitsignals when the system is turned OFF. For example, the STBY bus may beused to transmit signals for turning the system ON, such as signalsbetween a microprocessor and an IC which controls various power supplieswithin the system. Another use for the STBY bus may be to providecommunication between a microprocessor and an electrically-erasableprogrammable read-only memory (EEPROM). Systems may also include anotherIIC bus generally referred to as a run (“RUN”) bus, which is used totransmit signals when the system is turned ON. The terms “RUN” and“STBY” may also be used to refer to different system power supplies. Inparticular, a RUN supply refers to a power supply used when the systemis turned ON, while a STBY supply refers to a power supply used when thesystem is turned OFF. STBY supplies, however, may also provide powerwhen the system is turned ON.

Some systems do not provide electrical power to any system ICs, except amicro-controller and some select ICs, when the system is turned OFF.When such systems are turned ON, the micro-controller typically mustfirst turn ON the RUN supplies before attending to other systemfunctions. Once all, system power supplies are operating, themicro-controller can then communicate with ICs on the RUN bus. There areinstances, however, where it is necessary to communicate over a RUN busbefore the system power supplies are operating.

For example, one such instance relates to an arrangement wherein an ICon the RUN bus receives power from both a STBY power supply and a RUNpower supply. If a fault condition occurs in the system whereby the RUNpower supplies are lost, the IC may continue to receive power from theSTBY supply and not be aware of the fault condition. When the faultcondition is corrected and the RUN power supplies are restored, the ICis unaware of the changing condition and immediately reverts to theprevious operating condition. This may create undesirable loadingconditions that may cause dips in the power supply if the IC causesexcessive loading immediately after the power is restored. Under normalconditions, methods such as using boost circuitry or orderly power upprocedure may be utilized upon start up to prevent such voltage dips andensure orderly resumption to the operating condition. However, this maynot be possible if one or more ICs on the bus are unaware of the faultcondition and the micro-controller is unable to communicate with the ICsover the RUN bus.

In view of the above, it is desirable for the micro-controller tocommunicate with the various ICs coupled to the RUN bus when the RUNpower supplies are inactivated. However, various conditions may hindercommunication over the RUN bus before the RUN supplies are restored.First, due to the intrinsic substrate diode used for electrostaticdischarge (ESD) protection on input pins of ICs, it is often impossibleto communicate with one IC on the RUN bus while the other ICs are notpowered. Moreover, there are bus interface circuits to translate a 3.3volt logic level to a 5 volt logic level bus that inhibit communicationto a specific IC on the RUN bus with the RUN power supplies turned OFF.These conditions greatly hinder the ability to provide the necessary buscommunication. Accordingly, there is a need to overcome the foregoingobstacles and enable communication over a bus while one or more ICsconnected to the bus are in an unpowered state.

The present invention provides an apparatus and a method for overcomingthe problems discussed above. In particular, the present inventionprovides an apparatus and method that ensures that an integrated circuitcan communicate with other integrated circuits on a bus even whenanother integrated circuit on the bus is in an unpowered state.

In one aspect, the present invention is a circuit configuration,comprising: a bus coupled to a first power supply; a first integratedcircuit coupled to the bus; a second integrated circuit coupled to thebus; and a third integrated circuit coupled to the bus via an interfacecircuit, the third integrated circuit and the interface circuit eachbeing coupled to first and second RUN power supplies, respectively,wherein upon an occurrence of a fault condition that causes a loss ofthe RUN power supplies, the interface circuit controls the loadingplaced on the bus by the interface circuit and the third integratedcircuit in a manner that enables the first integrated circuit and thesecond integrated circuit to continue to communicate with each other viathe bus.

In another aspect, the present invention is a television apparatus,comprising: a bus coupled to a first power supply; an input forreceiving television signals; a display including deflection circuitry;a micro-controller coupled to the bus; a first processing circuitcoupled to the bus, the input and the display, the first processingcircuit receiving the television signals and generating output signalsto drive the display; a second processing circuit coupled to the bus viaan interface circuit, the second processing circuit and the interfacecircuit each being coupled to first and second RUN power supplies,respectively, wherein upon an occurrence of a fault condition thatcauses a loss of the RUN power supplies, the interface circuit controlsthe loading placed on the bus by the interface circuit and the secondprocessing circuit in a manner that enables the micro-controller and thefirst processing circuit to continue to communicate with each other viathe bus, whereby the micro-controller is able to turn OFF the firstprocessing circuit prior to reactivating the RUN power supplies.

The above-mentioned and other features and advantages of this invention,and the manner of attaining them, will become more apparent and theinvention will be better understood by reference to the followingdescription of embodiment of the invention taken in conjunction with theaccompanying drawings, wherein:

FIG. 1 is a block diagram of an exemplary television apparatus suitablefor implementing the present invention;

FIG. 2 is bus diagram illustrating the connection of the variousintegrated circuits to the microprocessor via the I2C busses;

FIG. 3 is a block diagram illustrating the connection of the variouspower supplies to the integrated circuits of FIG. 2;

FIG. 4 is a schematic diagram illustrating the connection of the variousintegrated circuits to the I2C bus via a bus interface circuit; and

FIG. 5 is a flowchart illustrating the operation of the circuitconfiguration of FIG. 4.

The exemplifications set out herein illustrate preferred embodiments ofthe invention, and such exemplifications are not to be construed aslimiting the scope of the invention in any manner.

Referring now to the drawings, FIG. 1 shows a block diagram of anexemplary television apparatus 100 for implementing the presentinvention. The structure and operation of the various elements oftelevision apparatus 100 as they relate to the processing of thetelevision signals are known to those skilled in the art and will not bedescribed in detail herein. Television apparatus 100 includes input 102,which receives RF television signals, e.g., from an antenna or cable,and applies the signals to one of main tuner 106 and second tuner 104.The output of main tuner 106 is provided to one chip color TV IC 120,which performs a number of functions associated with processing theinput video signal. One chip IC 120 is capable of performing the variousfunctions associated with a color TV system including, but not limitedto, sound IF and FM demodulation, audio volume control, video processingwith selectable on-chip lowpass filters, video processing withselectable bandpass filters, horizontal and vertical deflection control,external RGB switching and AKB functionality. One chip ICs are known inthe art and include, for example, LA7612N, manufactured by SanyoCorporation.

The composite video output from one chip IC 120 is applied to an inputof video switch 108. Video switch 108 also receives video inputs fromsecond tuner 104 and the AUX input, and selects the desired video signalin response to user input. The video signals associated with the mainand inset pictures are provided to FPIP IC 110, which combines the videosignals to provide the desired video display. The combined video signalis provided to one chip IC 120, which provides the further processing togenerate R, G, B, signals necessary to drive output circuit 126. Onechip IC 120 also provides control for the deflection circuitry bycontrolling vertical drive circuitry 154 and flyback circuitry 155. Onechip IC 120 also provides the separated audio signal to audio processor130, which generates the signals to drive speaker 132. Televisionapparatuses that employ such a structure include, for example, CTC 195,manufactured by Thomson multimedia Inc. of Indianapolis Ind.

Micro-controller 150 controls the overall operation of televisionapparatus 100 and coordinates the operation of the various integratedcircuits via the busses. Micro-controller also controls the overallON/OFF state of television apparatus 100 via power supply controlcircuitry 156. Suitable micro-controllers included, but are not limitedto, ST92196, manufactured by SGS Thomson.

The various integrated circuits associated with the television apparatusdescribed above are interconnected by RUN IIC bus 170 and STBY IIC bus180. As noted above, the IIC bus is a simple bi-directional 2 wire busthat provides for efficient inter IC control. The two wires, namelyserial data (SDA) and serial clock (SCL) lines, carry informationbetween the devices connected by the bus. Both SDA and SCL are normallyconnected to a positive supply voltage through a pull up resistor. Whenthe bus is in the free condition, both SDA and SCL are in the HIGHcondition. During data transfer, a designated master device generatesclock signals on the SCL line, and addresses a designated slave deviceto initiate data transfer to or from the designated slave device. Thedata on the SDA line must be stable during the HIGH state of the clock,and the HIGH and LOW state of the data line can only change when theclock signal on the SCL line is LOW.

As shown in FIG. 2, micro-controller 150 is coupled, via IIC RUN bus170, to FPIP IC 110, video switch 108, main tuner 106, one chip IC 120,second tuner 104, and service connector 172. Micro-controller 150 isalso coupled, via IIC STBY bus 180, to service connector 172 and EEPROM174. In the present embodiment, micro-controller 150 turns ON televisionapparatus 100 via power supply control circuitry 156. During start up,micro-controller 150 first turns ON the RUN power supplies before it canturn ON the horizontal deflection and the various components oftelevision apparatus 100. Once television apparatus 100 is turned ON andthe various power supplies are operating, micro-controller 150 cancommunicate with the various components on IIC RUN bus 170. However, asdiscussed further below, it may be necessary for micro-controller 150 tocommunicate with various ICs when the RUN supplies are inactive. Thepresent invention ensures that such communication is possible.

The arrangement of micro-controller 150 with respect to the variouspower is supplies and to the various ICs according to the presentinvention is shown in FIGS. 3 and 4. As shown in FIG. 3, the main 16Vsupply for the various regulators is derived from a tap on thetransformer that develops the 140V Reg B+. The primary side of SMT 160is controlled by SMT controller 159 via switch Q2. The 16V supply isprovided to the inputs of 7.5V STBY regulator 162, 7.5V RUN regulator164, 5V STBY regulator 166, and 12V RUN regulator 168. The outputs ofSTBY regulator 162 and RUN regulator 164 are applied to one chip IC 120.The output of STBY regulator 166 is applied to RUN bus 170 (“V1”) and tomicro-controller 150. The output of RUN regulator 168 is applied tointerface circuits 160 and 161 (“V2”) and to RUN regulator 169, which inturn supplies the necessary operating voltage for the 3.3V devices inthe apparatus, including FPIP IC 110. Micro-controller 150 controls theON/OFF state of RUN regulators 164 and 168 via power supply controlcircuitry 156. Finally, one chip IC 120 controls the deflectioncircuitry in part via switch Q1.

As noted above, one chip IC 120 is powered from both STBY regulator 162and RUN regulator 164. More specifically, the bus portions of one chipIC 120 is powered from STBY regulator 162 while the rest of the IC ispowered from RUN regulator 164. The 5V standby voltage is applied to IICRUN bus 170 through resistor R1.

FPIP IC 110 is coupled to RUN IIC bus 170, which comprises data line 200and clock line 202, as shown in FIG. 4. FPIP IC 110 includes an inputCLK_IN coupled to the clock line 202 via interface circuit 160 and inputDATA_IN coupled to data line 200 via interface circuit 161. FPIP IC 110also includes output DATA_OUT coupled to data line 200 via switch Q5.FPIP IC 110 receives the 3.3V operating supply from RUN regulator 169.An interface circuit is required to couple FPIP IC 110 to IIC RUN bus170 to allow interoperability between the FPIP IC and the IIC RUN bus.In particular, bus 170, micro-controller 150, tuner 106, video switch108, and one chip IC 120 are 5V devices. That is, they each use 5 voltsto represent a logic high state. By contrast, FPIP IC 110 is a 3.3Vdevice. Therefore, interface circuitry is required to translate 5V logicto 3.3V logic. Although FIG. 4 only illustrates elements 150, 106, 108,120 and 160 being coupled to IIC RUN bus 170, it is to be understoodthat additional ICs are coupled to IIC RUN bus 170 as well.

Interface circuitry 160 includes switch Q3, capacitor C2, and resistorsR3–7. Preferred values for C2 and R3–7 are 100 pf, 100 ohms, 6.8K ohms,180 ohms, 1 K ohms, and 4.7K ohms, respectively. The values of theelements of interface circuitry 160 are selected to ensure the desiredloading on IIC RUN bus 170 in the event that the RUN power supplies arelost.

As noted, a problem arises in the arrangement described above withregard to the ability of micro-controller 150 to communicate with thevarious ICs on IIC RUN bus 170 in the event of a fault condition thatcauses the loss of the RUN power supplies. If a fault condition occurs,such as a “watchdog” event, the RUN power supplies are turned OFF, andas such, the RUN portions of one chip IC 120 are also turned OFF.However, since the bus portions of one chip IC 120 are powered throughSTBY regulator 162, one chip IC 120 continues to operate as if in the ONstate. When the RUN power supplies are restored by micro-controller 150,one chip IC 120 immediately restores the drive for flyback in thedeflection circuitry since IC 120 is unaware of the previous faultcondition. As a result, the initial loading on the main switchmodesupply is greater than expected and causes the output of the switchmodetransformer SMT to dip, thereby causing a fault condition withintelevision apparatus 100. The dip in the output of the transformer SMTmay be prevented by the use of a boost circuitry as the flyback isactivated. However, since one chip IC 120 is not aware that a faultcondition has occurred and one chip IC 120 returns immediately to theprevious operating condition, no provisions are made to compensate forthis condition.

More specifically, power supply to regulators 162, 164, 166, and 168 arederived from an output of main switch mode transformer 160. The 16Vstandby supply is indirectly regulated by being on the same transformeras the 140V “regulated B+.” The regulation is good as long as the 140supply is loaded. When television apparatus 100 is turned OFF, the 140 Vload is removed and the supply to the regulators drops to about 12V.Depending on tolerances, this level may or may not allowmicro-controller 150 to start into the proper power down sequence. Boostcircuitry 163 may be added to work around this problem. Boost circuitry163 changes a resistor divider from the 140V supply into comparator 157that drives opto-isolator 158 that controls the primary of SMT 160. Whenthe 23V RUN supply off the flyback is active, boost circuitry 163 isinactive and the 140V supply is regulated at 140V. When televisionapparatus 100 is OFF, the 23V RUN supply is OFF and boost circuitry 163boosts the 140V supply to about 160V. During normal turn ON, boostcircuitry 163 remains active until the load of the 140V supply ispresent and stable. However, if the HDRIVE signal from one-chip IC 120is not turned OFF due a “watchdog reset,” kine-arc or ESD condition,boost circuitry 163 remains disabled. When micro-controller 150 comesout of the reset, and boost circuitry 163 is disabled, the 16V supplyfrom SMT 160 will sag to about 12V. This prevents micro-controller fromproperly turning on television apparatus 100.

To prevent such an undesirable condition, all of the ICs coupled to IICRUN bus 170 must be turned OFF prior to reactivation of the RUN powersupplies. Therefore, micro-controller 150 must be able to turn OFF onechip IC 120 via RUN IIC bus 170 when the fault condition occurs.However, a problem occurs due to the fact that the supply for interfacecircuitry 160 and 161 are provided by RUN regulator 168. When the RUNpower supplies are removed, the connection of RUN regulator 168 to thecollectors of switches Q3 and Q4 tends to pull down the voltage on buslines 200 and 202, respectively, thereby preventing communication viaRUN IIC bus 170.

The present invention overcomes the above by providing an apparatus andmethod for ensuring that micro-controller 150 can continue tocommunicate with one chip IC 120, via IIC RUN bus 170 and interfacecircuitry 160 and 161, even when the RUN power supplies are removed. Inparticular, the exemplary interface circuit establishes and maintains avoltage on IIC RUN bus 170 that is sufficient to enable micro-controller150 to communicate with one chip IC 120 when the RUN power supplies areremoved. The exemplary interface circuitry includes a means forcontrolling the loading on IIC RUN bus 170 caused by the interfacecircuit and FPIP IC 110 to a predetermined level upon the loss of theRUN power supplies, which predetermined level is sufficient to ensurethat micro-controller 150 can communicate with one chip IC 120. As such,micro-controller 150 is able to turn OFF one chip IC 120 even during afault condition and prior to restoring the RUN power supplies.

The operation of the circuit of FIG. 4, including interface circuitry160 and 161 is now described. Although the circuitry will be describedwith reference to interface circuitry 160, it is to be understood that asimilar description is applicable to the operation of interfacecircuitry 161.

When a fault condition occurs, RUN power supplies 164 and 168 becomeinactivated. In particular, the 12V supply to interface circuit 160(“V2”), the RUN supply to one chip IC 120 (“V4”), and the 3.3V RUNsupply to FPIP IC 110 become inactivated. Micro-controller 150 and thebus portions of one chip IC 120 continued to receive power through STBYregulators 166 and 162, respectively.

With regard to IIC RUN bus 170, the loading of clock line 202 isestablished as follows. As previously indicated, the voltage on bus line202 is approximately 5V when bus 170 is active, and the system uses 5Vto represent a logic high state. Accordingly, in order for bus line 202to mimic a state wherein television apparatus 100 is ON, the voltage onbus line 202 must represent a logic high state. In establishing thevoltage on bus line 202, the intrinsic diode from the base to collectorof transistor Q3 clamps the voltage on the base to 0.7 volts (assumingthe current in the 100 ohm resistor R3 is low). The pull-up for the baseof transistor Q3 is resistor R1, which is connected to the 5V STBYregulator 166. The voltage on bus line 202 is determined by resistorR1's 10K ohm pull-up to 5V, the drop across the 6.8K ohm resistor R4,and the base-collector voltage of transistor Q3 (which is approximately0.7 volts). Therefore, when the RUN supplies are inactive, the voltageon clock line 202 is approximately 2.5 volts. Since one chip IC 120 hasa voltage threshold of 2.4 volts for a logic high state, a bus linevoltage of 2.5 volts is sufficient to ensure that one chip IC 120 candetect a logic high state on clock line 202. Although the value ofresistor R4 is 6.8K ohms in the exemplary embodiment, the value ofresistor R4 may be selected as necessary to ensure that the loading onRUN bus 170 remains above the threshold required for one chip IC 120 torecognize a logic HIGH level. It can be seen that the value of resistorR4 may be selected as desired to control the loading of interfacecircuitry 160 and FPIP IC 110 during a fault condition. The desiredloading may be determined by the threshold voltage necessary for an ICon the bus to detect a high state.

To improve reliability, a “push-pull” mode of one chip IC 120 may beused. In this mode, the output voltage of micro-controller 150 islimited to 3.3V, but the drive impedence now becomes about 2K ohms,rather than 10 K ohms, working against R4+R3 plus the 0.7V from the basecollector junction of Q3. Using the push pull mode provides additionaldrive capability. The push pull mode is described in further detail inU.S. patent application Ser. No. 09/581,780, filed Nov. 9, 2000, whichis assigned to the assignee of the present invention and is incorporatedherein. Once the voltage on clock line 202, as well as data line 200, isestablished in the aforementioned manner, micro-controller 150 can acommand to one chip IC 120 over RUN bus 170 causing one chip IC 120 toturn OFF. By turning one chip IC 120 OFF before the RUN power suppliesare turned back ON, a fault condition is avoided.

FIG. 5 a flowchart illustrating the sequence during a fault and restartcondition for television apparatus 100 wherein various ICs of televisionapparatus 100 are placed in the OFF condition to ensure that properrestart of television apparatus can be performed. In step 200, a faultcondition is detected, and in response, the RUN power supplies areturned OFF in step 202. When the RUN power supplies are turned OFF, theinterface circuitry establishes a new voltage on bus 170 in step 204. Asdescribed above, the new voltage is sufficient to ensure thatmicro-controller 150 can communicate with one chip IC 120 in step 206.Once the various ICs, including one chip IC 120, have been turned OFF,micro-controller restores the RUN power supplies in step 208 during thestart up process.

Although the present exemplary embodiment describes the use of a onechip IC used in performing color TV functions, the present invention isapplicable to any circuit arrangements wherein an IC is coupled to a busvia an interface circuit, and wherein a fault condition may result inloading of the bus in a manner that may prevent communications via thebus. Furthermore, although described in relation to an exemplarytelevision apparatus, the present invention is applicable to any audio,video or other consumer electronics device, such as a video cassetterecorder (VCR), digital satellite receiver, digital video disc (DVD)player, compact disc player, computer, or similar system, wherein it maybe desirable to ensure communication over a bus as described.Furthermore, the present invention may be applied in the context ofdevices that are networked over a particular bus. In such a networkedenvironment, the loss of power to one device may result in loss of theability to communicate over the bus. Similar to the loading controlprovided by the interface circuitry of the present invention, the maininterface circuitry of the devices may be designed to limit the loadingto a predetermined level that permits the devices, or selected devices,on the bus to communicate with each other.

While this invention has been described as having a preferred design,the present invention can be further modified within the spirit andscope of this disclosure. This application is therefore intended tocover any variations, uses, or adaptations of the invention using itsgeneral principles. Further, this application is intended to cover suchdepartures from the present disclosure as come within known or customarypractice in the art to which this invention pertains and which fallwithin the limits of the appended claims.

1. A circuit configuration, comprising: a bus coupled to a first powersupply; a first integrated circuit coupled to the bus, the firstintegrated circuit recognizing a first predetermined voltage level aslogic HIGH level; a second integrated circuit coupled to the bus, thesecond integrated circuit recognizing the first predetermined voltagelevel as logic HIGH level; and a third integrated circuit coupled to thebus, wherein the third integrated circuit recognizes a secondpredetermined voltage, which differs from the first predeterminedvoltage level, as logic HIGH level, the third integrated circuit beingcoupled to the bus via an interface circuit that performs bi-directionallevel shifting to allow interoperability of the third integrated circuitwith the first and second integrated circuits, the third integratedcircuit and the interface circuit each being coupled to first and secondRUN power supplies, respectively, and wherein upon a fault conditionthat results in a loss of the RUN power supplies, the loading placed onthe bus by the interface circuit and the third integrated circuit iscontrolled to a level that enables the first integrated circuit and thesecond integrated circuit to continue to communicate with each other viathe bus.
 2. The circuit configuration of claim 1, wherein the secondintegrated circuit is coupled to a second power supply and a third RUNpower supply, and wherein during the fault condition the first, secondand third RUN power supplies are lost.
 3. The circuit configuration ofclaim 1, wherein the interface circuit comprises a bipolar transistorhaving a base coupled to the bus via a first resistor, a collectorcoupled to the second RUN power supply and an emitter coupled to anoutput of the third integrated circuit, and wherein the loading of theinterface circuit and the third integrated circuit on the bus during afault condition is determined in response to the value of the firstresistor.
 4. The circuit configuration of claim 1, wherein the bus is anIIC bus, the first integrated circuit is a 5V device and the thirdintegrated circuit is a 3.3V device.
 5. The circuit configuration ofclaim 4, wherein the loading on the bus is controlled to maintain atleast 2.5V on the bus during a fault condition when the RUN powersupplies are lost.
 6. A television apparatus, comprising: a bus coupledto a first power supply; an input for receiving television signals; adisplay including deflection circuitry; a micro-controller coupled tothe bus, the micro-controller recognizing a first predetermined voltagelevel as logic HIGH; a first processing circuit coupled to the bus, theinput and the display, the first processing circuit receiving thetelevision signals and generating output signals to drive the display,the first processing circuit recognizing the first predetermined voltagelevel as logic HIGH; a second processing circuit coupled to the bus;wherein the second processing circuit recognizes a second predeterminedvoltage level that differs from the first predetermined voltage level aslogic HIGH, the second processing circuit is coupled to the bus via aninterface circuit that translates voltage level to allowinteroperability of the second processing circuit with themicro-controller and the first processing circuit, the second processingcircuit and the interface circuit each being coupled to first and secondRUN power supplies, respectively, and wherein upon a loss of the RUNpower supplies, the loading placed on the bus by the interface circuitand the second processing circuit is controlled in a manner that enablesthe micro-controller and the first processing circuit to continue tocommunicate with each other via the bus, whereby the micro-controller isable to turn OFF the first processing circuit prior to reactivating theRUN power supplies.
 7. The television apparatus of claim 6, wherein theinterface circuit comprises a bipolar transistor having a base coupledto the bus via a first resistor, a collector coupled to the second RUNpower supply and an emitter coupled to an output of the secondprocessing circuit, and wherein the loading of the interface circuit andthe second processing circuit on the bus during a fault condition isdetermined in response to the value of the first resistor.
 8. Thetelevision apparatus of claim 7, wherein the first processing circuit isa one chip integrated circuit having a plurality of color TV functionsincorporated therein, including deflection circuitry control.
 9. Thetelevision apparatus of claim 8, wherein the first processing circuitincludes a bus portion coupled to a second power supply and a controlportion for controlling the deflection circuitry coupled to a third RUNpower supply.
 10. The television apparatus of claim 9, wherein the firstprocessing circuit is turned OFF via the bus in response to a faultcondition and prior to initiating a start up procedure, whereby anHDRTVE signal from the first processing circuit to the deflectioncircuitry is removed.
 11. The television apparatus of claim 10, whereinthe bus is an IIC bus, the micro-controller is a 5V device and thesecond processing circuit is a 3.3V device.
 12. The television apparatusof claim 10, wherein the micro-controller is coupled to a power supplycontrol circuitry that controls the ON/OFF state of the RUN powersupplies.
 13. The television apparatus of claim 10, wherein the firstprocessing circuit is capable of operating in a push pull mode ofoperation to increase the voltage on the bus during a fault conditionwhen the RUN supplies are lost.
 14. The television apparatus of claim10, further comprising a boost circuit operatively coupled to a sourcefor the first and second power supplies, the boost circuit capable ofbeing enabled when the IIDRIVE signal is absent.
 15. A network,comprising: a bus coupled to a first power supply; a first electronicdevice coupled to the bus, the first electronic device recognizing afirst predetermined voltage level as logic HIGH; a second electronicdevice coupled to the bus, the second electronic device recognizing thefirst predetermined voltage level as logic HIGH; and a third electronicdevice coupled to the bus, wherein the third electronic devicerecognizes a second predetermined voltage level that differs from thefirst predetermined voltage level as logic HIGH, the third electronicdevice being coupled to the bus via an interface circuit that translatesvoltage levels to allow interoperability between of the third electronicdevice with the first and second electronic devices, the thirdelectronic device and the interface circuit each being coupled to a RUNpower supply, and wherein upon a loss of the RUN power supply, theloading placed on the bus by the interface circuit and the thirdelectronic device is controlled in a manner that enables the firstelectronic device and the second electronic device to continue tocommunicate with each other.